A commonly used differential amplifier structure is an amplifier which has differential input transistors and a load transistor coupled to each differential input transistor to form a differential input stage. An output stage is coupled to the differential input stage. Many efforts have previously been directed toward the problem of correcting an inherent input offset voltage associated with the differential input transistors. Many of these efforts are layout techniques, such as laying out the differential input transistors to be invariant with respect to normal electronic mask misalignment, and providing four input transistors which are configured as two cross-coupled transistor pairs to minimize offsets due to process and temperature gradients. However, as noted by Paul Gray and Robert Meyer in "MOS Operational Amplifier Design-A Tutorial Overview" in the IEEE Journal of Solid-State Circuits, Volume SC-17, No. 6, December 1982, pages 969-982, another offset voltage contribution known as "systematic offset voltage" is a problem in operational amplifiers. Systematic offset voltage is an offset voltage which results from the requirement of a load transistor and an output transistor coupled thereto to have differing gate-source voltages, V.sub.GS , to insure that the quiescent output voltage of the output stage is substantially halfway between two supply voltages. Systematic offset voltage is also dependent on power supply voltage and reduces the amplifier's power supply rejection ratio. To overcome the systematic offset voltage, the current density in the load transistors and the output stage transistor needs to be equal so that when the same V.sub.GS exists across these transistors, the output will be substantially halfway between the two supply voltages. To force the transistors to have equal current densities, the physical geometries of the transistors are ratioed wherein the transistor gate lengths are made equal and the gate widths are ratioed accordingly. However, this gate length requirement degrades the operational amplifier performance because to obtain a low output noise level and a high low frequency gain, the gate lengths of the load transistors need to be made long, whereas the gate length of the output transistor needs to be made short to obtain a large transconductance, g.sub.m, and good output drive capability. Yet, if the gate lengths of the load transistors and the output transistor are not the same, any ratio of currents set up through the load transistors and the output transistor will vary with respect to processing and temperature. Therefore, previous differential amplifier circuits have not generally been able to provide an output voltage with no systematic offset voltage and optimum power supply rejection and noise and frequency characteristics because known solutions for a specific design feature have resulted in the degradation of other design features.